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Floating Point Unit
Floating point unit
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Computer arithmetic
(126)
Arithmetic logic unit
Barrel shifter
Decimal floating point
Double precision
Execution unit
Execution unit
Extended precision
Fixed point arithmetic
Floating point
IEEE 754
IEEE 854
Multiply-accumulate
Quadword
Sign bit
Significand
Single precision
2147483647
Adder (electronics)
Adder-subtractor
Additron Tube
Adjust flag
Arbitrary precision algorithms
Arbitrary-precision arithmetic
Arithmetic overflow
Arithmetic shift
Arithmetic underflow
Augmented assignment
Balanced ternary
Base 36
Bi-quinary coded decimal
Binary Integer Decimal
Binary and
Binary numeral system
Binary scaling
Binary-coded decimal
Bit manipulation
Bit numbering
Bitwise operation
Booth's multiplication algorithm
Carry (arithmetic)
Carry flag
Carry look-ahead adder
Carry operator
Carry-save adder
Chen-Ho encoding
Circular shift
Common operator notation
Compare-and-swap
Computer numbering formats
Computron Tube
Dadda multiplier
Data unit
Decimal128 floating-point format
Decimal32 floating-point format
Decimal64 floating-point format
Denormal number
Densely packed decimal
Direction flag
Division (digital)
Division by two
Division by zero
Excess-3
Exponent bias
Exponentiation by squaring
Fetch-and-add
Gal's accurate tables
Half precision floating-point format
Hamming code
Hamming(7,4)
Hexadecimal
IBM Floating Point Architecture
IEEE 754 revision
IEEE 754-1985
IEEE machine
ISO/IEC 10967
Interval arithmetic
Kahan summation algorithm
Kogge-Stone adder
Least significant bit
Logical shift
Long double
Long integer
Machine epsilon
Mask (computing)
Method of complements
Minifloat
Modulo operation
Montgomery reduction
Most significant bit
Multiplication ALU
Negative base
Negative flag
Normal number (computing)
Normalized number
Numerical error
Octal
Offset binary
Overflow flag
Q (number format)
Quadruple precision floating-point format
Radix point
Redundant binary representation
Residue number system
Rounding (The table-maker's dilemma)
SIGFPE
Saturation arithmetic
Serial binary adder
Serial decimal
Short integer
Sign extension
Sign-value notation
Signed number representations
Signed zero
Signedness
Subtractor
Symmetric level-index arithmetic
Technical Floating Point
Ternary numeral system
Test and Test-and-set
Test-and-set
Tetradecimal
Two's complement
Two-out-of-five code
Unit in the last place
Wallace tree
Wrapping (overflow)
Zero flag
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Primitive types
(14)
Address constant
Bit
Boolean data type
Byte
Character (computing)
Character (computing)
First-class function
Fixed point arithmetic
Floating point
Pointer (computing)
Primitive data type
Quadword
Reference (computer science)
String (computer science)
Word (computing)
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Data types
Floating point
Single precision
Fixed point arithmetic
Double precision
Quadword
Central processing unit
(73)
Bit slice
General purpose registers
Index registers
Instruction cache
Instruction set architecture
Instruction set architecture
Microarchitecture
Microprocessors
Processing unit
Accumulator (computing)
Advanced Load Address Table
Architectural state
Arithmetic logic unit
Barrel processor
Berkeley RISC
Bumpless Build-up Layer
CPU bound
CPU core voltage
CPU design
CPU locking
CPU modes
CPU power dissipation
CPU shielding
CPU sockets
CPU time
Cache coherency
Computer cooling
Control register
Cycle stealing
Datapath
Double fault
Dual-voltage CPU
Execution unit
FLAGS register (computing)
Flag (computing)
Flag word
Frequency scaling
Hardware performance counter
Hardware register
History of general purpose CPUs
Instruction unit
Link register
List of CPU architectures
List of instruction sets
Little man computer
Micro-operation
Microcode
Microcontroller
Minimal instruction set computer
Mobile processor
Motorola 68000 family
Multithreading
NX bit
Network Instruction Set Processor
Order code processor
Page (computer memory)
Parity flag
Program counter
Program status word
Reset vector
Ring (computer security)
Scalar processor
Speed-demon
Stack register
Static core
Status register
Stepping level
Stride scheduling
Teraflops Research Chip
Test register
Translation lookaside buffer
Voltage Identification Digital
Wait state
Zero instruction set computer
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Computer architecture
(72)
Addressing modes
Harvard architecture
Instruction processing
Power Architecture
Simultaneous multithreading
Simultaneous multithreading
Superscalar
ARM architecture
Abstraction layer
Address space
Advanced RISC Computing
Bridging model
Burroughs large systems descriptors
Cellular architecture
Classes of computers
Comparison of CPU architectures
Computer architecture simulator
Computer arithmetic
Computer hardware researchers
Consistency model
Cross-Platform Support Middleware
Dataflow
Dataflow architecture
Distributed computing architecture
Embryonics Project
Esção
Explicit Data Graph Execution
Extendable instruction set computer
Fault-tolerant computer systems
Flexible Architecture for Simulation and Testing
Flynn's Taxonomy
Fraglets
Frequency scaling
Hardware architect
Heterogeneous computing
Hybrid-core computing
IEEE Transactions on Computers
IOMMU
Instruction set architectures
Intel Tera-Scale
Interconnect processing unit
International Symposium on Computer Architecture
Interoperability
Interrupts
MIPS architecture
Memory ordering
Microarchitecture
Modified Harvard architecture
Multi-core
Multiprogramming
NEC SX architecture
Ne-XVP
Network Centric Product Support
Network architecture
NonStop
Open architecture
Operating system kernels
Operating systems by architecture
Popek and Goldberg virtualization requirements
Processor units
Processor-in-memory
Reference model
Semantic service oriented architecture
Single Point of Failure
Slot (computer architecture)
Stream processing
System bus model
Tagged architecture
Vaakya Architecture
Von Neumann architecture
Von Neumann syndrome
Zero address arithmetic
x86 architecture
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Instruction processing
(69)
Branch prediction
Clock cycle
Instruction cycle
Instruction pipeline
Instructions per cycle
Instructions per cycle
Out of order execution
Reorder buffer
Speculative execution
Applicatio- n-specific instruction-set processor
Barrel processor
Berkeley RISC
Branch misprediction
Branch predication
Branch target predictor
Bubble (computing)
Burroughs large systems instruction set
CEVA-X DSP
Classic RISC pipeline
Control store
DLX
Decoupled architecture
Degree of parallelism
Delay slot
Explicitly parallel instruction computing
GPGPU
Hardware scout
Hazard (computer architecture)
Instruction level parallelism
Instruction prefetch
Instruction set architecture
Instruction set matrix
Interlock (engineering)
Itanium
Jazelle
List of instruction sets
MIL-STD-1750A
MIPS architecture
Machine code
Memory barrier
Memory level parallelism
Micro-operation
Microarchitecture
Microcode
Minimal instruction set computer
Model-specific register
Multithreading
Native mode
Operand forwarding
Orthogonal instruction set
Pipeline (computing)
Prefetch input queue
Register window
Reservation stations
Reset vector
Runahead
ST200 family
Scoreboarding
Single cycle processor
Slipstream (computer science)
Speculative multithreading
Tomasulo algorithm
Transport triggered architecture
TriMedia (Mediaprocessor)
Unicore
Very long instruction word
XCore XS1
XCore XS1-G4
XCore XS1-L1
Zero instruction set computer
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Microprocessors
Direct Connect Architecture
SuperH
MPC5200
Instruction processing
Clock cycle
Instruction set architecture
Microarchitecture
SIMD computing
Single Instruction Multiple Data
Streaming SIMD Extensions
3dnow
Classes of computers
Complex instruction set computer
Reduced instruction set computer
Single Instruction Multiple Data
Superscalar
Harvard architecture
Digital electronics
Clock signal
Register file
Interrupt controller
External bus
Bit slice
Computer memory
Memory latency
Advanced Transfer Cache
EDRAM
Memory controller
Memory bandwidth
Direct memory access
Instruction cache
Motorola microprocessors
(14)
88110
PowerQUICC
68k microprocessors
88000
MPC5200
MPC5200
Motorola 6800
Motorola 6800 family
Motorola 6809
Motorola G5 project
Motorola MC14500B
PowerPC 600
PowerPC 7xx
PowerPC G4
PowerPC e200
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See also
(20)
Memory management unit
FPU
Branch instruction
Floating point operations per second
80387
80387
X87
Vector processing
AMD Virtualization
PowerPC 440
Coprocessor
DMIPS
Instructions per second
Mantissa
Microprocessor Report
Instruction code
68882
Renesas
On-chip debugging
Chip RAM
Clock gating
more...
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